Bulldog IT – 700001 – CPU

Summary Info

Processor(s)

Processor Name – Intel Xeon E5-2630 v4
Number Of Processor Packages (Physical) – 2
Number Of Processor Cores – 20
Number Of Logical Processors – 40
Original Processor Frequency – 2200.0 MHz
CPU Brand Name – Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz

Full Item Description

Bulldog IT – Report

BulldogIT.co.uk

Content:

CPU

BULLDOGIT-CO-UK

Central Processor(s)


[CPU Unit Count]
	Number Of Processor Packages (Physical):	2
	Number Of Processor Cores:	20
	Number Of Logical Processors:	40

Intel Xeon E5-2630 v4


[General Information]
	Processor Name:	Intel Xeon E5-2630 v4
	Original Processor Frequency:	2200.0 MHz
	Original Processor Frequency [MHz]:	2200

	CPU ID:	000406F1
	CPU Brand Name:	Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz
	CPU Vendor:	GenuineIntel
	CPU Stepping:	R0
	CPU Code Name:	Broadwell-EP
	CPU Technology:	14 nm
	CPU S-Spec:	SR2R7
	CPU Thermal Design Power (TDP):	85.0 W
	CPU Thermal Design Current (TDC):	98.0 A
	CPU Power Limits (Max):	Power = 170.00 W, Time = 40.00 sec
	CPU Power Limit 1 (Long Duration)/Processor Base Power (PBP):	Power = 85.00 W, Time = 1.00 sec [Unlocked]
	CPU Power Limit 2 (Short Duration)/Maximum Turbo Power (MTP):	Power = 102.00 W, Time = 7.81 ms [Unlocked]
	Configurable TDP Level 1 (Down):	85.00 W (21.00 W – 170.00 W), 1800 MHz
	Current Configurable TDP Level:	Nominal (Legacy) [Unlocked]
	CPU Max. Junction Temperature (Tj,max):	90 °C
	CPU Type:	Production Unit
	CPU Platform:	Socket R3 (LGA2011-3)
	Microcode Update Revision:	B000040

	Number of CPU Cores:	10
	Number of Logical CPUs:	20

[Operating Points]
	CPU MFM (Low Power):	800.0 MHz = 8 x 100.0 MHz
	CPU LFM (Minimum):	1200.0 MHz = 12 x 100.0 MHz
	CPU HFM (Base):	2200.0 MHz = 22 x 100.0 MHz
	CPU Turbo Max:	3100.0 MHz = 31 x 100.0 MHz [Unlocked]
	Turbo Ratio Limits – IA/SSE, Fused:	31x (1-2c), 29x (3c), 28x (4c), 27x (5c), 26x (6c), 25x (7c), 24x (8-10c)
	Turbo Ratio Limits – IA/SSE, Resolved:	31x (1-2c), 29x (3c), 28x (4c), 27x (5c), 26x (6c), 25x (7c), 24x (8-10c)
	Turbo Ratio Limits – AVX2, Fused:	31x (1-2c), 29x (3c), 28x (4c), 27x (5c), 26x (6c), 25x (7c), 24x (8-10c)
	Turbo Ratio Limits – AVX2, Resolved:	31x (1-2c), 29x (3c), 28x (4c), 27x (5c), 26x (6c), 25x (7c), 24x (8-10c)
	CPU Current:	3092.9 MHz = 31 x 99.8 MHz @ 1.0162 V
	LLC/Ring Maximum:	2700.0 MHz = 27.00 x 100.0 MHz
	LLC/Ring Current:	1197.2 MHz = 12.00 x 99.8 MHz

	CPU Bus Type:	Intel QuickPath Interconnect (QPI) v1.1
	Number of QPI Links per CPU:	2
	Maximum Supported QPI Link Clock:	4000 MHz (8.00 GT/s)
	Current QPI Link Clock:	4000 MHz (8.00 GT/s)

	CPU Bus Type:	Intel Direct Media Interface (DMI) v2.0
	Maximum DMI Link Speed:	5.0 GT/s
	Current DMI Link Speed:	5.0 GT/s

[IA Overclocking]
	Voltage Offset:	Not Supported
	Voltage Override:	Supported
	Ratio Overclocking:	Not Supported
	Fused Ratio Limit:	31x
	OC Ratio Limit:	N/A
	Voltage Mode:	Adaptive
	Voltage Offset:	0 mV
[CLR (CBo/LLC/Ring) Overclocking]
	Voltage Offset:	Not Supported
	Voltage Override:	Supported
	Ratio Overclocking:	Not Supported
	Fused Ratio Limit:	27x
	OC Ratio Limit:	N/A
	Voltage Mode:	Adaptive
	Voltage Offset:	0 mV
[Uncore/SA Overclocking]
	Voltage Offset:	Not Supported
	Voltage Override:	Not Supported
	Ratio Overclocking:	Not Supported
	Fused Ratio Limit:	N/A
	OC Ratio Limit:	N/A
	Voltage Mode:	Adaptive
	Voltage Offset:	0 mV
[Analog IO Overclocking]
	Voltage Offset:	Not Supported
	Voltage Override:	Not Supported
	Ratio Overclocking:	Not Supported
	Fused Ratio Limit:	N/A
	OC Ratio Limit:	N/A
	Voltage Mode:	Adaptive
	Voltage Offset:	0 mV

[Cache and TLB]
	L1 Cache:	Instruction: 10 x 32 KBytes, Data: 10 x 32 KBytes
	L2 Cache:	Integrated: 10 x 256 KBytes
	L3 Cache:	25 MBytes
	Instruction TLB:	2MB/4MB Pages, Fully associative, 8 entries
	Data TLB:	4 KB Pages, 4-way set associative, 64 entries

[Standard Feature Flags]
	FPU on Chip	Present
	Enhanced Virtual-86 Mode	Present
	I/O Breakpoints	Present
	Page Size Extensions	Present
	Time Stamp Counter	Present
	Pentium-style Model Specific Registers	Present
	Physical Address Extension	Present
	Machine Check Exception	Present
	CMPXCHG8B Instruction	Present
	APIC On Chip / PGE (AMD)	Present
	Fast System Call	Present
	Memory Type Range Registers	Present
	Page Global Feature	Present
	Machine Check Architecture	Present
	CMOV Instruction	Present
	Page Attribute Table	Present
	36-bit Page Size Extensions	Present
	Processor Number	Not Present
	CLFLUSH Instruction	Present
	Debug Trace and EMON Store	Present
	Internal ACPI Support	Present
	MMX Technology	Present
	Fast FP Save/Restore (IA MMX-2)	Present
	Streaming SIMD Extensions	Present
	Streaming SIMD Extensions 2	Present
	Self-Snoop	Present
	Multi-Threading Capable	Present
	Automatic Clock Control	Present
	IA-64 Processor	Not Present
	Signal Break on FERR	Present
	Virtual Machine Extensions (VMX)	Present
	Safer Mode Extensions (Intel TXT)	Present
	Streaming SIMD Extensions 3	Present
	Supplemental Streaming SIMD Extensions 3	Present
	Streaming SIMD Extensions 4.1	Present
	Streaming SIMD Extensions 4.2	Present
	AVX Support	Present
	Fused Multiply Add (FMA)	Present
	Carryless Multiplication (PCLMULQDQ)/GFMUL	Present
	CMPXCHG16B Support	Present
	MOVBE Instruction	Present
	POPCNT Instruction	Present
	XSAVE/XRSTOR/XSETBV/XGETBV Instructions	Present
	XGETBV/XSETBV OS Enabled	Present
	Float16 Instructions	Present
	AES Cryptography Support	Present
	Random Number Read Instruction (RDRAND)	Present
	Extended xAPIC	Present
	MONITOR/MWAIT Support	Present
	Thermal Monitor 2	Present
	Enhanced SpeedStep Technology	Present
	L1 Context ID	Not Present
	Send Task Priority Messages Disabling	Present
	Processor Context ID	Present
	Direct Cache Access	Present
	TSC-deadline Timer	Present
	Performance/Debug Capability MSR	Present
	IA32 Debug Interface Support	Present
	64-Bit Debug Store	Present
	CPL Qualified Debug Store	Present
[Extended Feature Flags]
	64-bit Extensions	Present
	RDTSCP and TSC_AUX Support	Present
	1 GB large page support	Present
	No Execute	Present
	SYSCALL/SYSRET Support	Present
	Bit Manipulation Instructions Set 1	Present
	Bit Manipulation Instructions Set 2	Present
	Advanced Vector Extensions 2 (AVX2)	Present
	Advanced Vector Extensions 512 (AVX-512) Foundation	Not Present
	AVX-512 Prefetch Instructions	Not Present
	AVX-512 Exponential and Reciprocal Instructions	Not Present
	AVX-512 Conflict Detection Instructions	Not Present
	AVX-512 Doubleword and Quadword Instructions	Not Present
	AVX-512 Byte and Word Instructions	Not Present
	AVX-512 Vector Length Extensions	Not Present
	AVX-512 52-bit Integer FMA Instructions	Not Present
	Secure Hash Algorithm (SHA) Extensions	Not Present
	Software Guard Extensions (SGX) Support	Not Present
	Supervisor Mode Execution Protection (SMEP)	Present
	Supervisor Mode Access Prevention (SMAP)	Present
	Hardware Lock Elision (HLE)	Present
	Restricted Transactional Memory (RTM)	Present
	Memory Protection Extensions (MPX)	Not Present
	Read/Write FS/GS Base Instructions	Present
	Enhanced Performance String Instruction	Present
	INVPCID Instruction	Present
	RDSEED Instruction	Present
	Multi-precision Add Carry Instructions (ADX)	Present
	PCOMMIT Instructions	Not Present
	CLFLUSHOPT Instructions	Not Present
	CLWB Instructions	Not Present
	TSC_THREAD_OFFSET	Present
	Platform Quality of Service Monitoring (PQM)	Present
	Platform Quality of Service Enforcement (PQE)	Present
	FPU Data Pointer updated only on x87 Exceptions	Not Present
	Deprecated FPU CS and FPU DS	Present
	Intel Processor Trace	Present
	PREFETCHWT1 Instruction	Not Present
	AVX-512 Vector Bit Manipulation Instructions	Not Present
	AVX-512 Vector Bit Manipulation Instructions 2	Not Present
	AVX-512 Galois Fields New Instructions	Not Present
	AVX-512 Vector AES	Not Present
	AVX-512 Vector Neural Network Instructions	Not Present
	AVX-512 Bit Algorithms	Not Present
	AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ)	Not Present
	AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ)	Not Present
	User-Mode Instruction Prevention	Not Present
	Protection Keys for User-mode Pages	Not Present
	OS Enabled Protection Keys	Not Present
	Wait and Pause Enhancements (WAITPKG)	Not Present
	Total Memory Encryption	Not Present
	Key Locker	Not Present
	57-bit Linear Addresses, 5-level Paging	Not Present
	Read Processor ID	Not Present
	OS Bus-Lock Detection	Not Present
	Cache Line Demote	Not Present
	MOVDIRI: Direct Stores	Not Present
	MOVDIR64B: Direct Stores	Not Present
	ENQCMD: Enqueue Stores	Not Present
	SGX Launch Configuration	Not Present
	Protection Keys for Supervisor-Mode Pages	Not Present
	Control-Flow Enforcement Technology (CET) Shadow Stack	Not Present
	Attestation Services for Intel SGX	Not Present
	AVX-512 4 x Vector Neural Network Instructions Word Variable Precision	Not Present
	AVX-512 4 x Fused Multiply Accumulation Packed Single Precision	Not Present
	Fast Short REP MOV	Not Present
	User Interrupts	Not Present
	AVX-512 VP2INTERSECT Support	Not Present
	AVX-512 FP16	Not Present
	MD_CLEAR Support	Present
	IA32_MCU_OPT_CTRL MSR Support	Not Present
	Restricted Transactional Memory (RTM) Always Abort	Not Present
	Restricted Transactional Memory (RTM) Force Abort	Not Present
	SERIALIZE	Not Present
	Hybrid Processor	Not Present
	TSX Suspend Load Address Tracking	Not Present
	Platform Configuration (PCONFIG)	Not Present
	Architectural LBRs	Not Present
	Indirect Branch Restricted Speculation (IBRS), Indirect Branch Predictor Barrier (IBPB)	Present
	Single Thread Indirect Branch Predictors (STIBP)	Present
	L1D_FLUSH Support	Present
	IA32_ARCH_CAPABILITIES MSR	Not Present
	IA32_CORE_CAPABILITIES MSR	Not Present
	Speculative Store Bypass Disable (SSBD)	Present
	Control-Flow Enforcement Technology (CET) Indirect Branch Tracking	Not Present
	Advanced Matrix Extensions (AMX) Tile Architecture	Not Present
	Advanced Matrix Extensions (AMX) bfloat16 Support	Not Present
	Advanced Matrix Extensions (AMX) 8-bit Integer Operations	Not Present
	SHA512 Instructions	Not Present
	SM3 Instructions	Not Present
	SM4 Instructions	Not Present
	Advanced Matrix Extensions (AMX) FP16 Instructions	Not Present
	AVX (VEX-encoded) Vector Neural Network Instructions	Not Present
	AVX-512 BFLOAT16 Instructions	Not Present
	Fast Zero-Length MOVSB	Not Present
	Fast Short STOSB	Not Present
	Fast Short CMPSB, SCASB	Not Present
	History Reset	Not Present
	Linear Address Masking	Not Present
	Linear Address Space Separation	Not Present
	RAO-INT Instructions	Not Present
	CMPccXADD Instructions	Not Present
	Flexible Return and Event Delivery (FRED)	Not Present
	LKGS Instruction	Not Present
	WRMSRNS Instruction	Not Present
	NMI-source Reporting	Not Present
	AVX-IFMA Instructions	Not Present
	RD/WR MSRLIST Instructions	Not Present
	INVD Execution Prevention After BIOS-Done	Not Present
	Protected Processor Inventory Number (IA32_PPIN) Support	Not Present
	PBNDKB Instruction	Not Present
	AVX-VNNI-INT8 Instructions	Not Present
	AVX-VNNI-INT16 Instructions	Not Present
	AVX-NE-CONVERT Instructions	Not Present
	PREFETCHIT0/1 Instructions	Not Present
	URDMSR/UWRMSR Instructions	Not Present
	AMX-COMPLEX Instructions	Not Present
	CET Supervisor Shadow-Stack	Not Present
	UIRET Support	Not Present
	Advanced Vector Extensions 10 (AVX10)	Not Present
	Advanced Performance Extensions (APX) Foundation	Not Present
	Not Exhibiting MXCSR Configuration Dependent Timing (MCDT)	Not Present
	UC-Lock Disable Feature	Not Present

[Enhanced Features]
	Thermal Monitor 1:	Supported, Enabled
	Thermal Monitor 2:	Supported, Enabled
	Enhanced Intel SpeedStep (GV3):	Supported, Enabled
	Bi-directional PROCHOT#:	N/A
	Extended Auto-HALT State C1E:	Enabled
	MLC Streamer Prefetcher	Supported, Enabled
	MLC Spatial Prefetcher	Supported, Enabled
	DCU Streamer Prefetcher	Supported, Enabled
	DCU IP Prefetcher	Supported, Enabled
	Intel Dynamic Acceleration (IDA) Technology:	Not Supported
	Intel Dynamic FSB Switching:	Not Supported
	Intel Turbo Boost Technology:	Supported, Enabled
	Programmable Ratio Limits:	Supported, Disabled
	Programmable TDC/TDP Limits:	Supported, Disabled
	Hardware Duty Cycling:	Not Supported
	Intel Speed Select:	Supported, Disabled

[CPU Scalable Features]
	GSSE256 Instructions:	Enabled
	AES:	Enabled
	LT SX (TXT for Servers):	Enabled
	LT Production:	Enabled
	SMX:	Enabled
	VMX:	Enabled
	VT-x3:	Enabled
	VT Real Mode:	Disabled
	VT CPAUSE:	Disabled
	Multi-Threading (HT):	Enabled
	Programmable TDP Limits:	Enabled
	EX Config:	Disabled
	EP 4S Config:	Disabled
	EP (1S/2S) Config:	Enabled
	EN (1S/2S) Config:	Disabled
	UP (1S/WS) Config:	Disabled
	Memory Channel Mirroring Mode:	Enabled
	Memory LT Support:	Enabled
	Memory Frequency Support:	DDR-2133
	Physical Address Size Supported (Core):	46-bit
	Extended APIC (x2APIC):	Enabled
	CPU HOT ADD:	Disabled
	GV3:	Enabled
	Core RAS (Data Poisoning, MCA Recovery):	Enabled
	DCA:	Enabled
	QPI Link 2:	Disabled
	QPI Link 1:	Enabled
	QPI Link 0:	Enabled
	Maximum Supported QPI Ratio:	8.0 GT/s
	NTB:	Enabled
	RAID-on-load:	Enabled
	PCIe LT SX:	Enabled
	PCIe LT:	Enabled
	PCIe Gen 3:	Enabled
	PCIe DMA:	Enabled
	DMI:	Enabled
	DDR4:	Enabled
	Monroe Technology:	Enabled
	SMBus Write Capability:	Enabled
	Extended Addressing DIMM:	Enabled
	Extended Latency DIMM:	Enabled
	Patrol Scrub:	Enabled
	Rank Sparing:	Enabled
	UDIMM Support:	Enabled
	RDIMM Support:	Enabled
	DIR:	Enabled
	ECC:	Enabled
	QR DIMM:	Enabled
	LOCKSTEP:	Enabled
	CLTT:	Enabled
	3N Mode:	Enabled
	4Gb DDR3:	Enabled
	8Gb DDR3:	Enabled
	Memory Channel 0:	Enabled
	Memory Channel 1:	Enabled
	Memory Channel 2:	Enabled
	Memory Channel 3:	Enabled
	CPU Stepping:	R0
	DRAM Power Meter:	Enabled
	DRAM RAPL:	Enabled
	PCIe Ratio for BCLK Overclocking:	Enabled
	Overclocking:	Disabled
	Energy Efficient Turbo:	Enabled
	Per-core P-states:	Enabled
	Uncore Frequency Scaling (UFS):	Enabled
	System Agent Power Management (SAPM) Dynamic Load Line (DLL):	Enabled
	Targeted SMI:	Enabled
	SMM CPU Save/Restore:	Enabled
	SMM Code Access Check:	Enabled
	Enhanced MCA:	Enabled
	FMA Instructions:	Enabled
	Hardware Lock Elison (HLE):	Enabled
	Hardware Lock Elison+ (HLE+)/RTM:	Enabled
	Voltage Override Overclocking:	Disabled
	Cache Allocation Technology (CAT):	Enabled
	Cache Monitoring Technology (CMT):	Enabled
	BCLK Coarse Ratio Support (PCIe Ratio Changing):	Enabled
	Physical Chop:	Low-Core Count (LCC)
	Product Type:	Broadwell
	PCIE Ratio Change:	Enabled
	VMCS Shadowing:	Enabled
	FIT Boot:	Enabled
	PFAT:	Enabled
	Error Spoofing:	Disabled
	COD:	Disabled
	Haswell New Instructions:	Enabled
	Second Home Agent:	Disabled

[Memory Ranges]
	Maximum Physical Address Size:	46-bit (64 TBytes)
	Maximum Virtual Address Size:	48-bit (256 TBytes)
[MTRRs]
	Range E0000000-100000000 (3584MB-4096MB) Type:	Uncacheable (UC)
	Range D0000000-E0000000 (3328MB-3584MB) Type:	Uncacheable (UC)
	Range 380000000000-380100000000 (58720256MB-58724352MB) Type:	Uncacheable (UC)
	Range CE000000-D0000000 (3296MB-3328MB) Type:	Uncacheable (UC)